1. Field of the Invention
The present invention relates to a nonvolatile memory and a method of programming the nonvolatile memory.
2. Discussion of the Related Art
Generally, for nonvolatile semiconductor memory devices for mass storage media such as EEPROM and flash EEPROM, the drawback that is the most difficult to overcome is the high cost-per-bit of the memories. In order to solve such a problem, studies on multibit cell have been recently proposed.
The packing density of a conventional nonvolatile memory corresponds in a one to one fashion to the number of memory cells. A multibit cell stores data of over two bits in one memory cell, thus enhancing the density of data on the same chip area without reducing the size of the memory cell.
For the multibit cell, more than three threshold voltage levels should be programmed on respective memory cells. For instance, in order to store data of two bits for every cell, the respective cells must be programmed in 2.sup.2, that is, four, threshold levels. Here, the four threshold levels correspond to logic states 00, 01, 10, and 11, respectively.
In the multi-level program, the most critical problem is that the respective threshold voltage levels have a statistical distribution. The distribution value is about 0.5 V.
As distribution is reduced by precisely adjusting the respective threshold levels, more levels can be programmed, which in turn increases the number of bits for every cell. To reduce the voltage distribution, there exists a method of programming using repeated programming and verification.
According to this method, a series of voltage pulses are applied to the cells in order to program the nonvolatile memory cell at intended threshold levels. To verify whether a cell reaches an intended threshold level, a read operation is performed between the respective programming voltage pulses.
During verification, when the verified threshold level reaches the intended threshold level, programming stops. For this method of repeated programming and verification, it is hard to reduce the error distribution of the threshold level due to the limited pulse width of a program voltage. In addition, the algorithm of repeated programming and verification is implemented with an additional circuit, which increases the area of peripheral circuits of the chip. Furthermore, the repetitive method prolongs the programming time. In order to solve such a drawback, R. Cernea of SunDisk Co., Ltd. suggested a method of simultaneous programming and verification.
FIG. 1A illustrates the symbol and circuit diagram of the nonvolatile memory proposed by Cernea. As shown in FIG. 1A, the nonvolatile memory cell is composed of a control gate 1, floating gate 2, source 3, channel area 4, and drain 5.
When voltages sufficient to cause programming are applied to control gate 1 and drain 5, a current flows between drain 5 and source 3. This current is compared to a reference current and when the current reaches a value equal to or smaller than the reference current, a programming completion signal is produced.
The above-mentioned procedure is illustrated in FIG. 1B. According to this prior art, verification is automatically performed at the same time as programming, which compensates for the drawbacks of the repetitive method in which programming and verification are repeated in succession.
However, in Cerneal's method, a program gate for programming is not used separately. Further, this method does not use a structure in which a programming current path and sensing (or verifying) current path are completely separated. For this reason, in Cernea's method, programming and sensing are difficult to optimize individually. The programming current and monitoring current are not separated so that the cell's threshold voltages are difficult to control and adjust directly. Conventionally, however, multi-level programming has been performed in such a manner that the voltages applied to the respective parts of a memory cell are fixed, and reference currents corresponding to the respective levels are varied. In this method, as shown in FIG. 1B, reference currents for detection have no explicit relation with the cell threshold voltages, and are not linear with them.
The cell structure of an EEPROM or a flash EEPROM is roughly divided into two parts, depending upon where the floating gate is placed on the channel area. The first structure is a simple-stacked gate structure in which the floating gate completely covers the cell channel area. The second one is a split-channel structure in which the floating gate covers only part of the channel area between the source and drain.
In the channel area, a portion where the floating gate is not present is called a transfer transistor, which is introduced to eliminate over-erasure problem. The split-channel cell is undesirably larger than the simple-stacked gate structure.
Another classification type of flash EEPROM depends on whether a double polysilicon gate or triple polysilicon gate is used. The double polysilicon gate is usually employed in the simple-stacked structure. The triple polysilicon gate is used in the split-channel cell. The EEPROM or flash EEPROM memory cells are disclosed in detail in U.S. Pat. No. 5,268,318. Conventionally, the third gate in the triple polysilicon gate is an erasing gate used merely for data erasure. In the flash EEPROM, erasure is performed in units of blocks made up of a plurality of cells.
FIG. 2A is a diagram of a conventional nonvolatile memory cell having a simple-stacked gate. FIG. 2B is a diagram of a conventional nonvolatile memory cell having a split-channel structure. FIGS. 2A and 2B show programming and erasing processes as well as the structure of the conventional nonvolatile memory cells.
As shown in FIG. 2A, the conventional stacked gate memory cell includes a control gate 6, a floating gate 7, a source 8, a drain 9, a channel area 10, and an erasing gate 11. As shown in FIG. 2B, the conventional split channel memory cell includes a control gate 13, a floating gate 14, a source 15, a drain 16, a channel area 17, and an erasing gate 18.
In FIGS. 2A and.2B, erasing gates 11 and 18 are not required for programming. Therefore, during programming, the conventional cells of FIGS. 2A and 2B have substantially the same structure as the double polysilicon gate.
In the prior art, programming is carried out only with the control gate, source, and/or drain electrodes so that it is difficult to separate the program current path and verification (sensing) current path within the memory cell for simultaneous programming and verification. Accordingly, it is difficult to control the multi-levels directly and effectively.